What is Φ0, and Φ2

Those are data clocks. I don't know about Asteroids specifically, but generally speaking PHI_0 comes from the clock generator. It goes into the processor and serves as the master timing reference for the system. PHI_2 is very similar to PHI_0 (usually just a small delay, with possibly a duty cycle change) Sometimes PHI_2 is generated by the clock generator but some processors actually generate PHI_2 themself from PHI_0. Either way, PHI_2 is sent to peripherals so that they know when addresses and data are valid. PHI_2 is the important one from the system point of view.
 
Ok, looks like on the 6502 Processor Φ0, and Φ2 come from the 6502 processor pins 37, and 39.

Trying to figure out how to hook up a cat box to and Asteroids board. Have not been able to find a catbox guide for the Asteroids board.

I did find a guide to using the HP 5004a, but it looks like the sigs are going to be different, but that might because I'm using a different rev board than what was originally done with the Hp5004a
 
Phi0 is the master clock input from the clocking circuit... Phi1 and Phi2 are outputs from the 6502.

IIRC, Phi1 is an inverted and delayed version of Phi0, and Phi2 is an inverted and delayed version of Phi1, so Phi2 just looks like a delayed Ph0.
 
IIRC, Phi1 is an inverted and delayed version of Phi0, and Phi2 is an inverted and delayed version of Phi1, so Phi2 just looks like a delayed Ph0.
That is basically correct for the 6502. I didn't know if Asteroids had a 6502 or 6809. If you want to troubleshoot a 6502 system, Phi2 is the data clock. Use that for the "clock" signal on a logic analyzer, etc.

I believe the details go like this:
Phi1 = ~Phi0 (with a small delay)
X (internal signal) = Phi0 & Phi1 (with a small delay)
Phi2 = X (with a small delay)

This gives you quasi-non-overlapping clocks internally and builds in a few delays for Phi2 to guarantee that the address bus is stable during the Phi2 falling edge. Total delay from Phi0 to Phi2 is something like 30ns but the duty cycle is somewhat different because of the delayed AND function. That's intentional.
 
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