Sucha deal!
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Yes I did.Did you get it? Congrats if you did and if not, I hope someone on here managed to get it.
I'm sure his phone beat you to the punchLooking forward to receiving my finders-fee.![]()
Yes I did.
Two weeks and no pics?
Is this really current pricing on 6809e pod?
SOLD - PARTS - Fluke 9010A(keeping), Z80 pod(keeping), 6502 pod(Sold), and 6809 pod(Sold)
My life has changed a bit over the last 3 years, and simply don't have time to do the deep dives in game boards like I used to. Get ready for sticker shock. Looking for 4K for the lot. 9010a works fine, probably looks better than most. 6502 pod looks good, works fine (I used to use it a lot)...forums.arcade-museum.com
I was thinking of selling my spare.
Does anyone have ROM dumps of the Fluke 9000A Pod Test Fixtures they can share?
I think there were 5 initially of these test fixture, maybe more. I know of 8080, 8085, Z80, 6502 and 6802.
They plugged into the Pod self test socket and the UUT cable plugged into them. They provided a known, minimal, UUT with test points. I am thinking of making a modern repro of them to assist with troubleshooting and fixing Pods.
| Pod (PCB) | PCB | Description |
| Z80 A11 | A11 | Processor PCB Assembly |
| Z80QT A11QT | A11QT | Processor PCB Assembly |
| Z80 A12 | A12 | Interface PCB Assembly |
| Z80QT A12QT | A12QT | Interface PCB Assembly |
| 8085 A13 | A13 | Processor PCB Assembly |
| 8085 A14 | A14 | Interface PCB Assembly |
| 6502 A15 | A15 | Processor PCB Assembly |
| 6502 A16 | A16 | Interface PCB Assembly |
| 8080 A17 | A17 | Processor PCB Assembly |
| 8080 A18 | A18 | Interface PCB Assembly |
| 9900 A19 | A19 | Processor PCB Assembly |
| 9900 A20 | A20 | Interface PCB Assembly |
| 6802 A21 | A21 | Processor PCB Assembly |
| 6802 A22 | A22 | Interface PCB Assembly |
| 6809 A23 | A23 | Processor PCB Assembly |
| 6809 A24 | A24 | Interface PCB Assembly |
| 8048 A25 | A25 | Processor PCB Assembly |
| 8048 A26 | A26 | Interface PCB Assembly |
| 8086 A27 | A27 | Processor PCB Assembly |
| 8086 A28 | A28 | Interface PCB Assembly |
| 8088 A28 | A28 | Interface PCB Assembly |
| 1802 A29 | A29 | Processor PCB Assembly |
| 1802 A30 | A30 | Interface PCB Assembly |
| 68000 A31 | A31 | Processor PCB Assembly |
| 68000 A32 | A32 | Interface PCB Assembly |
| Z8000 A33 | A33 | Processor PCB Assembly |
| Z8000 A34 | A34 | Interface PCB Assembly |
| 8088 A35 | A35 | Processor PCB Assembly |
| 6800 A36 | A36 | Processor PCB Assembly |
| 6800 A37 | A37 | Interface PCB Assembly |
| 8051 A38 | A38 | Processor PCB Assembly |
| 8086 A38 | A38 | Processor PCB Assembly |
| 8051 A39 | A39 | Interface PCB Assembly |
| 8086 A39 | A39 | Interface PCB Assembly |
| 8088 A39 | A39 | Interface PCB Assembly |
| 80186 A40 | A40 | Processor PCB Assembly |
| 8088 A40 | A40 | Processor PCB Assembly |
| 80186 A41 | A41 | Interface PCB Assembly |
| 80188 A41 | A41 | Interface PCB Assembly |
| 80188 A42 | A42 | Processor PCB Assembly |
| 80286 Clock | PCB | Clock Buffer Assembly |
| 80286 Intf | PCB | Interface PCB Assembly |
| 80286 Proc | PCB | Processor PCB Assembly |
@JRR John Robertson is the only person I know who has these. AFAIU they were never a product, Fluke internal for their test centers. There was also software for each (on tape). John posted about them on the TTL but I can't seem to find the thread anymore. Pictures and PDFs are here: ftp://ftp.flippers.com/TTL/TestEquipment/Fluke/9XXX Pods/PodTestFixtures (FTP only, no HTTP).
If someone ends up sharing the ROM/tape data hopefully they will advocate for any resulting Gerbers being made freely available. The boards themselves are rather simple.
Thanks John, much appreciated.If anyone is tinkering with the test fixture cards or thinking of making any I've updated the photos and added the EPROM files:
ftp://ftp.flippers.com/TTL/TestEquipment/Fluke/9XXX Pods/PodTestFixtures
Note that the Test Fixture tapes are hiding in:
ftp://ftp.flippers.com/TTL/TestEquipment/Fluke/9010 Series/9010A Tapes
Any questions?
John :-#)#
;Fluke Z80 Pod Test Fixture EPROM Code 652669 V1.1
;
;The Z80 Test Fixture plugs into the Pod Self Test socket. It only uses power and clock from the Pod socket.
;The Pod UUT Cable plugs into the Z80 socket on this fixture, making it the UUT. Running from the Pod power and Clock.
;
;The EPROM is enabled during /MREQ cycles when A11 is low. A10-A0 and D7-D0 map to EPROM A10-A0, D7-D0.
;There are pullup/pulldown resistors that place 0CFH on the data bus, whenever the EPROM is not selected.
;All Z80 control inputs are pulled high, making them inactive.
;
;There is a resistive voltage divider and switch to simulate a powerfail using the fixture.
;
;This EPROM code is used during RUN UUT to exercise certain address and data lines on the Pod
;
;The code uses jumps, to several addresses, to toggle certain high order address bits during instruction fetches.
;It uses read and write instructions to toggle address lines above the EPROM space.
;
;There are three seperate tests in the EPROM, one each for Reset, IRQ and NMI
;The Pod Reset signal is initially driven by the Pod and executes the Reset test when RUN UUT (at taddress 0) is started
;Reset places the Z80 in Interrupt Mode 0, which requires a program byte be placed on the data bus when IRQ is toggled.
;When IRQ is toggled and the CPU executes the Interrupt Acknowledge, the pullup/pulldown 0CFH data is read. 0CFH is a RST 08H insctruction.
;When NMI is toggled the code jumps to address 66H.
;
;For completeness the unused bytes in the ROM are 0FFH. This is a RST 38H instruction, which would go to invalid code if executed.
;
;The IRQ and NMI tests are accessed by manually pulsing the respective Z80 or test pins low after Reset.
;
;There is no RAM, which for the Z80 means no stack space
;When an allowed Interrupt occurs it pushes the interrupt routine return address to nowhere
;
;There are Jump to self loops after each piece of code.
;These are to try and keep the Z80 looping at one spot if there is an error.
;
;The address lines exercised by each test are as follows (A6 to A0 to be confirmed):
; A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
;RESET A13,A12, A11, A5 --- to ----- A0
;IRQ A14, A12, A8, A7, A5 --- to ----- A0
;NMI A15, A10,A9, A6,A5, A3 -- to A0
;
.ORG 0000H ;Interrupt vector for Reset routine
Reset0: JP Reset1
IRQ0: .ORG 0008H ;Interrupt vector for IRQ
JP IRQ1
;Reset routine executed after Pod Resets or RUN UUT start address
;Routine will run through program code and jumps to stay in Reset4 loop after reset, until an interrupt.
;As per theory of operation, toggles A0-A6,A11,A12,A13. As per code, toggles A13,A12,A11,A5-A0
Reset1: EI ;Enable IRQ interrupt
Reset4: LD A,00H
LD (1000H),A ;Write 1000H to toggle A12. Write 00H to toggle data lines low
LD A,(0800H) ;Read 800H to toggle A11. Reads idle bus 0CFH
JP Reset2
JP $
Reset2: JP Reset3
JP $
Reset3: LD (2000H),A ;Write 2000H to toggle A13. Write 0CFH, read from previous read
JP Reset4
JP $
.ORG 0030H
;IRQ routine only executed if IRQ manually toggled, then stays in IRQ4 loop
;IRQ routine will disable interrupts, so can be activated run once
;As per theory of operation, toggles A0-A6,A12,A14. As per code, toggles A14,A12,A8,A7,A5-A0
IRQ1: DI
IRQ4: LD A,00H
LD (1000H),A ;Write 1000H to toggle A12. Writes 00H to toggle data lines low
LD A,(1000H) ;Write 1000H to toggle A12
JP IRQ2
JP $
.ORG 0066H
;Interrupt vector for NMI, only executed if NMI manually toggled, then stays in NMI1 loop
;As per theory of operation, toggles A0-A6,A10,A15. As per code, toggles A15,A10,A9,A6,A5,A3-A0
NMI0: JP NMI1
.ORG 0080H ;IRQ routine at 80H to toggle A7
IRQ2: JP IRQ3
JP $
.ORG 0100H ;IRQ routine at 100H to toggle A8
IRQ3: LD (4000H),A ;Write at 4000H to toggle A14
JP IRQ4
JP $
.ORG 0200H ;NMI routine at 200H to toggle A9
NMI1: JP NMI2
JP $
.ORG 0400H ;NMI routine at 400H to toggle A10
NMI2: LD (8000H),A ;Write at 8000H to toggle A15
JP NMI1
JP $
.END
;Fluke 8080 Pod Test Fixture EPROM Code 540229 V1.1
;
;Refer to Z80 Test Fixture EPROM Code for more general information
;Using Z80 Mnemonics (8080 codes only, binary compatible). This allows changes and the use of a Z80 assembler
;
;There are 3 switches on the fixture to simulate power fails on all 3 voltage rails
;
;All control lines are tied inactive through either pullup or pulldown resistors as needed
;
;Address range decode outside EPROM has pullups for 0FFH on the data bus. 0FFH is a Rst 38H instruction.
;Empty EPROM locations are filled with 0FFH, a Rst 38H instruction. This is executed if code goes off the rails.
;
;The address lines exercised by each test are as follows:
; A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
;RESET A14,A13, A11, A5 --- to ----- A0
;IRQ A15, A13,A12, A10 ------------ to ------------ A0
.ORG 0000H ;Interrupt vector for Reset routine
;Reset routine executed after Pod Resets or RUN UUT start address
;Routine will run through program code and jumps to stay in Reset0 loop after reset, until an interrupt.
;As per code, toggles A14,A13,A11,A5-A0
Reset0: EI ;Enable IRQ interrupt
LD A,00H
LD (2000H),A ;Write 2000H to toggle A13. Write 00H to toggle data lines low
LD A,(0800H) ;Read 800H to toggle A11. Reads idle bus 0FFH
JP Reset1
JP $
.ORG 0010H ;Reset routine at 10H to toggle A4
Reset1: JP Reset2
JP $
.ORG 0020H ;Reset routine at 20H to toggle A5
Reset2: LD (4000H),A ;Write 4000H to toggle A14
JP Reset0
JP $
.ORG 0038H ;Interrupt vector for IRQ
;IRQ routine only executed if IRQ manually toggled, then stays in IRQ5 loop
;IRQ routine will disable interrupts, so can be activated only once after reset
;As per code, toggles A15,A13,A12,A10-A0
IRQ0: DI
IRQ5: LD A,00H
LD (2000H),A ;Write 2000H to toggle A13. Write 00H to toggle data lines low
LD A,(1000H) ;Read 100H to toggle A12. Reads idle bus 0CFH
JP IRQ1
JP $
.ORG 0080H ;IRQ routine at 80H to toggle A7
IRQ1: JP IRQ2
JP $
.ORG 0100H ;IRQ routine at 100H to toggle A8
IRQ2: JP IRQ3
JP $
.ORG 0200H ;IRQ routine at 200H to toggle A9
IRQ3: JP IRQ4
JP $
.ORG 0400H ;IRQ routine at 400H to toggle A10
IRQ4: LD (8000H),A ;Write 8000H to toggle A15
JP IRQ5
JP $
.END