Taito Zarzon cocktail table repair

No...
Because as I've said twice already, it isn't getting configured properly by the CPU.
my apologies, I misunderstood.

I probe the reset on the 6502 CPU and find it is high (not in reset) and the clock inputs are banging away. I probe the first four bits of the address on pins 9-12 and they are held high.

are there any obvious signs of a dead CPU? Or another suspect supporting circuit?

1760109285183.png
 
I've had some test equipment issues but still on this... I find a ~700kHz clock on the tri-state gate (2G_bar, for 74LS244... output enabled when low) pins 19 of IC 3 and 4 (ch 2, blue). Pin 1 (ch1, yellow) is held high (bank 1 output disabled, ie, CPU is outputting data.
NewFile2.png

I measure the CPU voltage D0 on pin 33 (ch1, yellow) and pin 26 (not shown, but behaves similarly) to be approximately this, alongside the clock from before:
NewFile1.png
NewFile0.png

I think this should suggest a short somewhere, but I don't know if I can say it's a problem with the output of the 6502 or the input of the 74LS244... but my initial thoughts are that it is more likely that the CPU is damaged than both IC3 and IC4 are displaying the same fault.

Is there anything I've missed? I could break the connection to one of the ICs and see if there's a proper square wave on the output of this pin without the connection; I probed this point with the CPU out of the socket, but of course, as the CPU is outputting, I read 0V with it missing.

I am also a bit concerned by the way the high clock pulse and the low D0 output have the same slope
 
Last edited:
I realized I could bend out the CPU pin from the socket to isolate it from the circuit. It turns out I was wrong about the data direction; there's no voltage on the splayed out pin, and the signature is still there from before at the IC4 point. Here I probe the output at pins 2,3 (ch 1, yellow) and the input pin 17,18 (ch2, blue) on IC4
PXL_20251022_013336884.jpg
NewFile4.png
The input does not seem to be an appropriate level, which makes the output logic level look bad. I will continue to search for clues upstream from here.

Edit: chip select on ROM 8 is the only one that's low on this board. Runt edges as shown in blue above are seen on D0, D1, D2, D3, and D7. I'll review the schematic & probe around the data bus on both boards.
 
Last edited:
Removing ROM 8 and probing the data 0 line again:
NewFile5.png
 
The 6502 gets the reset vector from $FFFC which maps into ROM8 and actually starts running code at $9700 in ROM10.

You're probably stuck in /RESET or /NMI or /IRQ.
 
The 6502 gets the reset vector from $FFFC which maps into ROM8 and actually starts running code at $9700 in ROM10.

You're probably stuck in /RESET or /NMI or /IRQ.
Thank you for the help I will go learn about those parts of the chip
 
I measure IRQ, RST, and NMI to all be steadily held high.

Yesterday I asked copilot how the 555 timer was configured and it said it was astable multivibrator, but I suspected that was wrong, so I threw it into LTspice. When you change the default rise/fall times of the pulse component in LTspice (doh) you see it is monostable, as you might expect from how you want the reset circuit to behave.

I observe the applied 5V power on ch2 in blue and the reset pin on the CPU on channel 1 in yellow.
NewFile6.png

Here I probe directly on the output of the 555 pin 3 (and swapped the channels :26:)
NewFile7.png
The datasheet indicates that reset should be held low for two clock cycles, which I don't think is an issue since it's low for ~500ms... Is this too long? should it be getting an IRQ before this? My simulation showed it should only be in reset for ~50ms, though I'm not sure how the diode alters the basic monostable circuit you find in a textbook. Analytic solution suggests the RC values should produce a 52ms pulse.

Edit: I think the output level on the 555 should suggest something is borked. This is probably what is altering the timing. However, I don't know what the failure mode would be to produce this... Tomorrow I'll try to capture the IRQ that I miss while in reset which would drive home this as the failure. Thanks again for the help.
 
Last edited:
I don't see any missing edges on /IRQ or /NMI while in reset- but I observe the circuit on the board is slightly different than the schematic I have:
PXL_20251023_160559902.jpg
The diode on the left that is piggybacking the 100k resistor is not shown in the schematic. Additionally, the 4.7k resistor in the schematic is populated with a 47kOhm- I think this would explain the timing discrepancy between the calculated pulse time and the measurement. So, I conclude this is probably not the problem circuit.
Screenshot 2025-10-23 091012.png
I would expect that the noise on the data lines is something I should chase down next? since there's noise on the data bus with ROM8 disconnected, it could be that the reset vector is never read properly to begin with, so it doesn't jump to $9700 in ROM10?
 
I have removed the graphics board via two connectors and it seems I'm still stuck in reset (indicated by ROM8 CS low) and the runt edges still appear. Clock on blue ch2; IC4 pin 17 (data 0) on yellow ch1.
NewFile5.jpg

I remove ROM8 and now there's a repeating pattern, mostly below the threshhold voltage.

NewFile6.jpg

Any ideas where to look next?

I could remove everything from the data bus except ROM8/ROM10?
 
Last edited:
Back
Top Bottom