Stargate CMOS RAM Problem?

cpyne

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Hi Everyone,

My Stargate has started throwing adjustment failure errors every time I start it up. If I then open the front door and start it, the settings clear and I can advance it to the normal start screen, but the high score table is all garbled. At this point it will make the coin sound if I put a credit in, but the credit count doesn't go up. If I press advance and cycle through the self test, I get a CMOS write protect error.

The power supply is the original, but I've replaced all the capacitors and connectors. I'm getting 5.05v on the CPU board.

Based on this, do you think replacing the CMOS chip is the best next step? Just want to get some expert feedback before I start replacing stuff...

The worst part is my high score is now gone!!!

Self test error...
http://i596.photobucket.com/albums/tt46/cpyne/cmos_error.jpg

High score screen....
http://i596.photobucket.com/albums/tt46/cpyne/bad_high_scores.jpg

Thanks
Charlie
 
Thanks. My followup question regarding the 3 things suggested...

Yellowdogs suggestions...
(1) the CMOS is indeed bad and needs to be replaced.
(2) the memory protect switch (front left side of the coin door) might be bad.
(3) the chips that sense the memory protect switch might be bad.



#2 - I know the switch is good since the machine behaves differently when I boot it with the door open vs closed. (goes to adjustment failure screen vs. lets you advance)

#3 - Because of the behavior seen in #2, can I assume the chips that sense the protect switch are also ok? (if so, then I'm thinking that #1 is the answer)
 
errors.

Thanks. My followup question regarding the 3 things suggested...

Yellowdogs suggestions...
(1) the CMOS is indeed bad and needs to be replaced.
(2) the memory protect switch (front left side of the coin door) might be bad.
(3) the chips that sense the memory protect switch might be bad.



#2 - I know the switch is good since the machine behaves differently when I boot it with the door open vs closed. (goes to adjustment failure screen vs. lets you advance)

#3 - Because of the behavior seen in #2, can I assume the chips that sense the protect switch are also ok? (if so, then I'm thinking that #1 is the answer)

EDIT: Apologies, musta been overtired the other night because i was reading the defender sheet by mistake. chip and pin references were wrong and circuit is slightly diff in stargate. need to revise my notes.
 
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Thanks. My followup question regarding the 3 things suggested...

Yellowdogs suggestions...
(1) the CMOS is indeed bad and needs to be replaced.
(2) the memory protect switch (front left side of the coin door) might be bad.
(3) the chips that sense the memory protect switch might be bad.



#2 - I know the switch is good since the machine behaves differently when I boot it with the door open vs closed. (goes to adjustment failure screen vs. lets you advance)

#3 - Because of the behavior seen in #2, can I assume the chips that sense the protect switch are also ok? (if so, then I'm thinking that #1 is the answer)

and in short have re-reviewed your question above, most likely yes but check first anyway!
 
You might also try removing the batteries while the game is powered down, wait 5 seconds and power up with the front door open. This should force the High Score Table, the Bookkeeping and the Game Settings to be reset.

If the High Score Table is still showing garbage after all this, it may well be the CMOS RAM. If the HST is good, while the game is still powered up, put the batteries back in. Then power the game down, wait a minute and then check the voltage on the CMOS chip (pin 18 is the supply voltage, pin 9 is the ground). If it is less than 2V you may have a battery holder problem or a dead battery rather than bad CMOS. The validity check on the game settings, the HST & the Bookkeeping is not very robust. It can get fooled by random values in the CMOS. The game settings tend to be the more robust of the 3 so they will get reset most frequently. Often the HST will be completely trashed and the POST will not even reset it. By pulling the batteries, you should force the POST to reset all three tables.

If the pulling the batteries trick doesn't work, then it will take working through the logic circuits to verity that the write protect is working correctly and that the CMOS chip is really the culprit.

ken
 
Sorry for introducing my request here, but i have a question very related to this thread.
Having a similar problem on my joust, i had to follow the instructions Andykmv suggested. With the front door closed (the back door one is always grounded), i gave a check on 5B: with one end on the main ground of the PCB and the other on PIN 3 i had approx 2V... does this means that my front door switch is bad ? Consider that i gave a continuity check to the switch and it gave continuity when pushed, so it's strange to me that the switch has the resistance causing the voltage drop. In addition, the machine behaves as it should when I boot it with the door open vs closed (and than gives me reboots on the HST).
 
Sorry for introducing my request here, but i have a question very related to this thread.
Having a similar problem on my joust, i had to follow the instructions Andykmv suggested. With the front door closed (the back door one is always grounded), i gave a check on 5B: with one end on the main ground of the PCB and the other on PIN 3 i had approx 2V... does this means that my front door switch is bad ? Consider that i gave a continuity check to the switch and it gave continuity when pushed, so it's strange to me that the switch has the resistance causing the voltage drop. In addition, the machine behaves as it should when I boot it with the door open vs closed (and than gives me reboots on the HST).


Apologies: musta been overtired the other night because i was reading the defender sheet by mistake, again!. chip and pin references i gave were wrong and circuit is slightly diff in stargate. please ignore my notes and i have a bad case of the fuzzies some wont revise my notes tonight.. :eek::eek:
 
Being a worldwide forum makes unespected things happen :)

No apologies are needed, the effort is very appreciated however (at least by me) :). I will wait for the correction than (and remember there is also a joust owner with similar problem reading this ;) ).
 
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Hi everyone - thanks for the info. I decided to take the advice of doing a bit more digging before I start swapping parts.

Frirst I tried yellowdog's suggestion of just pulling the batteries. This didn't fix it. The high score table still holds the same mess.

I then used a logic probe and traced what is happening at the points between the door switch input and the cmos chip 1C. Here are the results.

____________Door Open___Door Closed
1J2-1...............High...............Low
6E Pin 4............High...............Low
6E Pin 6............High...............Both
IC1 Pin 9...........High...............Both
IC1 Pin 8...........Both...............Both
(IC1 Pin 10).......Both...............Both
(IC1 Pin 11).......Both...............Both
1C Pin 10..........Both...............Both

I'm not really sure if this means IC1 is doing something wrong since nothing is getting past it or if its just doing what it's told based on the inputs into pins 10 and 11. Can anyone give any advice?

Also, does it seem normal that the door closed condition starts out as just low on the first two test spots, but then changes to "both" at the pin 6 output of 6E?

Thanks
Charlie

PS - Here's a link to this section of the board if anyone doesn't have a manual handy. (Also, if it matters, mine is the board version that has the small daughter board attached.)
http://i596.photobucket.com/albums/tt46/cpyne/SCAN0002.jpg
 
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IC1 is a 3 input NAND gate. basically an AND gate with the output inverted. what it means is that when ANY of the inputs are LOW the output pin 8 is HIGH. when ALL of the inputs are HIGH the output is low. if for example two inputs are HIGH and one is pulsing the output will be pulsing. eg with coin door open R43 pulls the mem protect line 1J2-1 high, so the input into 6E beocmes high. as 6e is an OR gate, its output becomes high therefore ic1-9 becomes high, AND as the Q clock is HIGH 1 million times a second, AND the R/W line is pulsed by the CPU during read/write opes, output IC1-8 will also pulse.

looks like that gate of IC1 is working fine.
 
____________Door Open___Door Closed
1J2-1...............High...............Low
6E Pin 4............High...............Low
6E Pin 6............High...............Both
IC1 Pin 9...........High...............Both
IC1 Pin 8...........Both...............Both
(IC1 Pin 10).......Both...............Both
(IC1 Pin 11).......Both...............Both
1C Pin 10..........Both...............Both

Also, does it seem normal that the door closed condition starts out as just low on the first two test spots, but then changes to "both" at the pin 6 output of 6E?

when the coin door is closed the mem protect interlock switch is shorted between 1J2-1&3 so it is grounded. therefore 6e pin 4 should be LOW. address lines A8 &A9 that are inputs to 6g pins 1 & 2 are used for many addresses in the whole system and as 6g is an OR gate its output pin 3 will always be pulsing in time with either A8 &r A9. therefore 6e's input pin 5 wil always be pulsing and as 6e is an OR gate it's output pin 6 will always be pulsing unless the coin door is open, so whilst the door is open 6e input pin 4 is held high so 6e ouput pin 6 will be held high, until the coin door closes whereupon it will go back to pulsing. therefore in answer to your question, yes it is normal for 6e output to be BOTH (ie pulsing).
 
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Aaaahhh.... Thanks for the explanation. The logic probe results make a lot more sense now.

One thing i don't fully understand is what is the general purpose for having the memory protect circuit in the first place? If I understand this correctly, it locks out the CPU from writing to the memory when the door is open. Why is this important? Also, how can changes to the game settings be written to the ram via the advance button if the ram is in write protect mode?

Thanks for humoring my rookie questions. :)
 
....One thing i don't fully understand is what is the general purpose for having the memory protect circuit in the first place? If I understand this correctly, it locks out the CPU from writing to the memory when the door is open. Why is this important? Also, how can changes to the game settings be written to the ram via the advance button if the ram is in write protect mode?:)

have a look at the manual "defender theory of operation ..." page 26 under CMOS RAM.

the game logic deals with the cmos ram memory space in two sections, the upper 128 and the lower 128. when the coin door is open the upper 128 can be changed, otherwise it is protected. keep in mind that an operator would have made game settings adjustments and do bookkeeping with the coin door open.
 
Thanks Andy. I jjust checked out the defender manual as well as the Stargate one. I didn't even notice this earlier, but the error LEDs displays some numbers while the CMOS self test is run. Acording to the Stargate manual, "3" and then "2" = "CMOS RAM FAILURE" and "3" and then "1" = "CMOS INTERLOCK FAILURE". Mine is showing "3"-"1" during the self test.

Based on what we saw with the logic probe tests, it looked like the interlock was good. At this point I was ready to swap the ram out, but do you think the "3-1" that I'm seeing could indicate other problems?
 
Acording to the Stargate manual, "3" and then "2" = "CMOS RAM FAILURE" and "3" and then "1" = "CMOS INTERLOCK FAILURE". Mine is showing "3"-"1" during the self test.

Based on what we saw with the logic probe tests, it looked like the interlock was good. At this point I was ready to swap the ram out, but do you think the "3-1" that I'm seeing could indicate other problems?

the flowchart in the manual also suggests replacing the address decoder 4G but you could test the output of 4g at pin 7 to see if it is pulsing, then followi that to inverter 5A input pin 1, and output pin 2 (reverse of pin 1) - test both the input and utput - if the output is pulsing then test IC1 -input 3 comes from 5A, so if the input is pulsing on 3 & 4 thats good. if the input to ic 1 at pin 5 (thats the q clock from the CPU)is pulsing thats good. if both pin 3 & 5 are pulsing at the same time then the output pin 6 should also be pulsing. if output pin 6 on ic1 is not pulsing at all then replace ic1.
last thing is Q1. rest the voltage across R65. if that is above 2v, it is HIGH the transistor Q1 should turn on, which allows the ChipSelect (/CS) to be driven by IC1 pin 6. if the output of IC1 pin 6 is not passing through Q1 then replace Q1.
Phew!

in short, if all else is working as expected, then replace the cmos ram (but put in a socket if it doesnt already have one, a good dual wipe socket!).
 
Being a worldwide forum makes unespected things happen :)

No apologies are needed, the effort is very appreciated however (at least by me) :). I will wait for the correction than (and remember there is also a joust owner with similar problem reading this ;) ).

hey dude! see my posts above re the cmos ram circuits for stargate - the chip refs are diff between joust and stargate too but the circuit is the same - it was redrawn a little neater for joust but you should be able to follow both and translate the chip nos. mind you i couldve just listed the transalations for you but got a headache as a result of doing my last post =)D
 
Thanks Andy, following this thread and the one i started i can now "read" my joust schematics and "translate" infos from the defender manual and topics on this forum. Thanks also to Ken, obviously :)
 
the flowchart in the manual also suggests replacing the address decoder 4G but you could test the output of 4g at pin 7 to see if it is pulsing, then followi that to inverter 5A input pin 1, and output pin 2 (reverse of pin 1) - test both the input and utput - if the output is pulsing then test IC1 -input 3 comes from 5A, so if the input is pulsing on 3 & 4 thats good. if the input to ic 1 at pin 5 (thats the q clock from the CPU)is pulsing thats good. if both pin 3 & 5 are pulsing at the same time then the output pin 6 should also be pulsing. if output pin 6 on ic1 is not pulsing at all then replace ic1.
last thing is Q1. rest the voltage across R65. if that is above 2v, it is HIGH the transistor Q1 should turn on, which allows the ChipSelect (/CS) to be driven by IC1 pin 6. if the output of IC1 pin 6 is not passing through Q1 then replace Q1.
Phew!

in short, if all else is working as expected, then replace the cmos ram (but put in a socket if it doesnt already have one, a good dual wipe socket!).

I just went and tested these points. There's no pulse at 4G Pin7 or the rest of the points down the line, (except for the clock signal at IC1 Pin5). Everything just shows a high signal. Could this point to a bad 4G? Here's what I see on 4G...

Pulse - 1 ## 16 - High
Pulse - 2 ## 15 - High
Pulse - 3 ## 14 - Pulse
High - 4 ## 13 - Pulse
Pulse - 5 ## 12 - High
Pulse - 6 ## 11 - High
High - 7 ## 10 - High
Low - 8 ## 9 - High
 
in my previous post quoted above, change "ChipSelect (/CS) to be driven by IC1 pin 6" to read
"...ChipSelect (/CS) to be driven HIGH or LOW by IC1 pin 6 thru Q1".

4G functionality: firstly the 74LS139 is a general purpose high speed decoder that is used in this instance to decode the CMOS RAM memory address. the IC has two independent decoder devices inside it. conveniently pins 1-8 are for one decoder, and pins 9-15 are for the second decoder. pin 16 is 5v, pin 8 is ground.

we are only concerned with the IC power supply (pins 8,16) & the 1st decoder (pins 1-7). pins 2&3 are the addressing pins, pin 1 is the enable pin , and pins 4,5,6,7 are the outputs, only one of which is active LOW at any one time (the pins 4-7 are normally HIG when INACTIVE and LOW when ACTIVE) when the ENABLE pin 1 is HIGH all outputs incl pin 7 remain HIGH (inactive). when the enable pin 1 is LOW, then the outputs are decoded from the address inputs on pins 2,3 to the relevant output (selected output is is driven LOW).

you said:
..I .. tested these points. ..no pulse at 4G Pin7 or the rest of the points down the line,
..(except for the clock signal at IC1 Pin5). Everything just shows a high signal.
..Could this point to a bad 4G? Here's what I see on 4G...
..STATE..PIN..FUNCTION...........(for clarity i have removed the irrelevant items)
..Pulse...1...ENABLE
..Pulse...2...Address A10
..Pulse...3...Address A11
..High....4...Output 0 - dont care
..Pulse...5...Output 1 - N/C
..Pulse...6...Output 2 - dont care
..High....7...Output 3 - the important pin
so, if Pin 7 is staying HIGH, then the input to 5A pin 1 is HIGH & output pin 2 is LOW. therefore IC1 input pins 3&4 are
LOW which means IC1 output pin 6 will stay LOW. TEST the voltage across R65. it is normally 5v (or HIGH) to ensutre that the /RESET is HIGH. then the input pin 5 of IC1 will be high, but unless 4g pin 7 drops LOW IC1 pin 6 wont change to LOW.

ok, having set the scene here, and if nothing is happening on these lines, then we need to look at where in the
game program we need to be for this situation to change. when you did the above test, were you
- in a game/attract mode with the coin door closed,
- in a game/attract mode with the coin door open, or
- in bookkeeping/test mode with the coin door open ?


in answer to your question, we may be in the wrong mode during testing as pin 7 is not being driven LOW.
if not in bookkeeping/test mode, then do so and retest, and repost results (incl the output of 5A p2, input IC1 pin 5 and IC1 output pin 6 too).
 
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