Divider Tests
The divider circuit on the Main PCB is an unsigned 15-bit fractional divider which assumes that the dividend (numerator) is less than twice the divisor (denominator). The hardware consists of a dividend latch, a dividend shift register, a divisor inverting latch, an adder, a difference latch, a quotient shift register with tri-state buffer, and a divider control which includes a divide cycle counter. Refer to the detailed block diagram on Sheet 5B to aid in understanding the circuit operation.
The dividend latch is written into by the microprocessor and has two parts: the dividend latch high byte (DVDDH) and the dividend latch low byte (DVDDL). The dividend latch is not altered by the operation of the divider so it may be left at its previous value, if desired.
The divisor latch is also written into by the microprocessor and has two parts: the divisor high byte (DVSRH) and the divisor low byte (DVSRL). The DVSRH line loads the divisor high byte, clears the quotient shift register, and loads the dividend shift register from the dividend latch. The DVSRL line loads the divisor low byte and starts the divider.
The divider subtracts the divisor from the dividend in the dividend shift register and puts the result in the difference latch. If the result of this subtraction is positive, the carry (C16*) will be a "1." The "1" is shifted into the quotient shift register, and the value from the difference latch is stored into the dividend shift register. (In a conventional divider algorithm, the dividend shift register would then be shifted to the left, but here the output of the adder is wired to the difference latch which is already shifted to the left.) If the result of the subtraction is negative, the carry (C16*) will be a "0." The "0" is shifted into the quotient shift register and the dividend shift register shifts once to the left. The value in the difference latch is otherwise ignored.
The following Test 21 through 25 determines the condition of the divider circuit. The test number will be shown on the display (assuming that the display and the AVG PCB are working). Each test is retriggered every 50 to 60 microseconds for as long as the test is selected.
Perform the Preliminary Procedure under Hardware Diagnostic Tests and set the option switch at location 10D on the Main PCB as indicated in the test.
The Mathbox Tests self-test display performs Hardware Diagnostic Test 21 through 25. The Mathbox Tests display shows the Option switch setting of any test that fails to produce the correct results.
Test 21
Tests for 15 pulses at pin 10 of divide cycle counter at location 8P.
Option Switch Setting:
87654321ONONONONOFFOFFOFFOFF
4000 (Dividend)/4000(Divisor) = 4000 (Quotient)
Test 22
Tests for shorted bits in the dividend and/or quotient.
Option Switch Setting:
87654321ONONONONOFFOFFOFFON
5555 (Dividend)/4000(Divisor) = 5555 (Quotient)
Test 23
Tests for shorted bits in the dividend and/or quotient.
Option Switch Setting:
87654321ONONONONOFFOFFONOFF
2AAA (Dividend)/4000(Divisor) = 2AAA (Quotient)
Test 24
Tests for shorter bits in the divisor. The data is inverted and appears at the outputs of the divisor inverting latch at location 4P, 5P, 6P, and 6L.
Option Switch Setting:
87654321ONONONONOFFOFFONON
2AAA (Dividend)/2AAA(Divisor) = 4000 (Quotient)
Test 25
Tests for shorter bits in the divisor. The data is inverted and appears at the outputs of the divisor inverting latch at location 4P, 5P, 6P, and 6L.
Option Switch Setting:
87654321ONONONONOFFONOFFOFF
5555 (Dividend)/5555(Divisor) = 4000 (Quotient)