SOIC vs TSSOP chips

shilmover

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Working on a project. Can anyone tell me the difference between the two chip types?

Is SOIC just a regular DIP chip with Surface Mount pins vs through hole pins?

Thanks!
 
Both are surface mount.

SOIC = Small Outline IC. This is just a run-of-the-mill surface mount part, usually dual in-line. Lead pitch is 0.98mm.

TSSOP = Thin Shrink Small Outline Package. About half the thickness of a SOP or SOIC and a lead pitch of 0.65mm. These usually come in a quad package, or pins on four sides instead of two.

HTH

Thanks!

So SOIC and DIP are NOT the same size?
 
Both are surface mount.

TSSOP = Thin Shrink Small Outline Package. About half the thickness of a SOP or SOIC and a lead pitch of 0.65mm. These usually come in a quad package, or pins on four sides instead of two.

Ugg, I hate those....but BGA are worse. What the hell were they thinking when they came up with BGA's ??

Edward
 
Ugg, I hate those....but BGA are worse. What the hell were they thinking when they came up with BGA's ??

I/O density. That was according to a guy I know who works for a fabless semi-house. Interestingly.. he said the bottom line was their BGA parts cost more to package than getting the same parts in QFP-144 packaging, however the BGA parts had about 2x the available I/O (!) Cost may also be because 'everyone' wants BGA packaging too.

- James
 
jrok,

I also work for a fabless semi. house and the added cost in bga comes from extra process step's to add a layer of metal called rdl (redistrubution layer) that would allow the original silicon i/o's to be redistributed to the solder balls that are now located in a grid pattern (2 x 3, 5 x 5, etc.) This also adds quite a bit of process time.


In packaging of components that are in plastic, as I am sure you know, the i/o's are connected to a leadframe via a gold bond wire.
 
I also work for a fabless semi. house and the added cost in bga comes from extra process step's to add a layer of metal called rdl (redistribution layer) that would allow the original silicon i/o's to be redistributed to the solder balls that are now located in a grid pattern (2 x 3, 5 x 5, etc.) This also adds quite a bit of process time.

Thank you for the update ;)

- James
 
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