I have a RAM failing the memory test on an Outrun project and hit a wall so I thought I'd throw what I'm seeing out here in case anyone has some ideas.
Below is what I am seeing. The red trace is one of the data lines on the shared data bus between 2 EPROM, 2 RAM, and at least 3 bus transceivers. That sawtooth is on D0-D15, but there is no trace of it on any address lines.

The green trace is on the other side of a bus transceiver going into data line of a 68000. I think the third pulse is a glitch causing the RAM failure that occurs when the sawtooth is high enough to change the state of the transceiver.
One thought i had is that one of the ICs on the bus has some leakage on its pins when it is tri-stated. But it would need to be leaking pretty heavy to drive the voltage up when another IC is driving it low. The other thought was that the chip select logic is jacked up, but it seems to check out. Could one of the ICs have a bad chip select or output enable input that is not tri-stating the data lines?
I removed any socketed chips to rule them out as the source, but I don't want to socket everything on the bus if there is a less invasive way to approach this.
Below is what I am seeing. The red trace is one of the data lines on the shared data bus between 2 EPROM, 2 RAM, and at least 3 bus transceivers. That sawtooth is on D0-D15, but there is no trace of it on any address lines.

The green trace is on the other side of a bus transceiver going into data line of a 68000. I think the third pulse is a glitch causing the RAM failure that occurs when the sawtooth is high enough to change the state of the transceiver.
One thought i had is that one of the ICs on the bus has some leakage on its pins when it is tri-stated. But it would need to be leaking pretty heavy to drive the voltage up when another IC is driving it low. The other thought was that the chip select logic is jacked up, but it seems to check out. Could one of the ICs have a bad chip select or output enable input that is not tri-stating the data lines?
I removed any socketed chips to rule them out as the source, but I don't want to socket everything on the bus if there is a less invasive way to approach this.




