I have the feeling that U6 could be the reason.
The photos are not good enough to let me read the imprint on the chip, but I assume it's the serial EEPROM holding the FPGA config and the did a little change to move the port.
J1 looks like a JTAG connector to program the serial EEPROM in circuit.
[UPDATE]
Yes, it is a serial EEPROM, but likely only holds HIGH SCORE and CONFIG.
J1 seems to be a JTAG, but the two chips with the heatsink are not FPGAs they are just CPLDs and CPLDs hold the firmware or schematics how ever you will call it inside.
Without a dump there is likely no other way then the patch
[/UPDATE]