Looking for some help on a CPU board repair.
I've spent some time over the past few days repairing 3 PP2 sets, and 2 PP1 video boards and I'm stuck on the last board, which is a PP2 CPU board.
I need some help from anyone knowledgeable on the CPU boot sequence. I'd like to confirm it's the watchdog interupting before CPU A resets as opposed to an issue in the CPU A Reset circuit itself.
Here's some info:
PP2 CPU board (Atari)
• on my bench setup, known good
• power is good
• Video board good
• interconnect board good
• all socketed chips good
• some sockets replaced but not all, but pretty sure that's not the issue.
• typical alkaline damage repaired, new parts installed, all confirmed good
• Z80 and CPU B both reset, but CPU A (@3A) does not get a reset (stuck low) and it's not an issue with the LS259 @8E
• when I manually reset CPU A (5v to lifted leg 14) the data lines all come alive so I think the general watchdog kicks in before CPU A's Reset kicks in. I think chasing a CPU A reset problem would be a red herring.
Does anyone know the actual CPU boot sequence? Does CPU B (@4N) boot before CPU A (@3A)? Is it: Z80 then B then A? If yes, then watchdog kicks in before it gets to A.
I've probed around and rams appear good, I know the ROMs and customs are good. The PAL at 5C (and 7C) is good. Not able to get to Self Test so that's no help.
Thoughts?
I've spent some time over the past few days repairing 3 PP2 sets, and 2 PP1 video boards and I'm stuck on the last board, which is a PP2 CPU board.
I need some help from anyone knowledgeable on the CPU boot sequence. I'd like to confirm it's the watchdog interupting before CPU A resets as opposed to an issue in the CPU A Reset circuit itself.
Here's some info:
PP2 CPU board (Atari)
• on my bench setup, known good
• power is good
• Video board good
• interconnect board good
• all socketed chips good
• some sockets replaced but not all, but pretty sure that's not the issue.
• typical alkaline damage repaired, new parts installed, all confirmed good
• Z80 and CPU B both reset, but CPU A (@3A) does not get a reset (stuck low) and it's not an issue with the LS259 @8E
• when I manually reset CPU A (5v to lifted leg 14) the data lines all come alive so I think the general watchdog kicks in before CPU A's Reset kicks in. I think chasing a CPU A reset problem would be a red herring.
Does anyone know the actual CPU boot sequence? Does CPU B (@4N) boot before CPU A (@3A)? Is it: Z80 then B then A? If yes, then watchdog kicks in before it gets to A.
I've probed around and rams appear good, I know the ROMs and customs are good. The PAL at 5C (and 7C) is good. Not able to get to Self Test so that's no help.
Thoughts?




