Neo Geo MVS 6 Slot - Stubborn Watchdog and Click of Death

trossi

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Neo Geo MVS 6 Slot - Stubborn Watchdog and Click of Death

Hi Everyone,

Looking for some assistance in troubleshooting a very stubborn 6 Slot with Click of Death. Been working on this one for a few weeks now and have not been able to identify the source of the problem. Did a lot of searching on KLOV and Google but have not found anything that matches up to what I am seeing unfortunately.

- Board had very light acid damage, I patched the 3 traces that run through that area
- Continuity between ROM, CPU and RAM for all Address and Data Lines
- No physical board damage, traces are looking good (other than acid lines above)
- VIAs look and test fine. Didn't test them all of course, but all I did test were fine
- ROM is UniBIOS and works fine in other MVS boards I have
- Replaced Backup and Work RAM chips
- Replaced 68k CPU
- Clock signal to 68k looks solid (Used my scope for this)
- No chips running hot (was hoping to find a shorted chip)
- All testing is without the top board connected. My other 6 slot boots to the crosshatch without the top board connected, so assuming its ok to troubleshoot without top board connected.

Watchdog continues to reset.

The only sign of a problem I can locate is that my logic probe is showing extremely weak Address lines A5 and up. A1-A4 show solid High. The other address lines cause my logic probe to just barely register a faint click and a very faint high LED blip during the watchdog reset. I can't locate the source of the short/drain on those address lines. There are a couple of 244's and 05's that also show the low logic level at their inputs. Pulled those chips and they test just fine. No trace damage in those areas, continuity looks ok.

Would anyone have a list of troubleshooting steps to follow at this point? I'm stumped as to where the problem lies. There must be more connected to the A5 and higher address lines that i'm missing. If any photos are needed, let me know and I'll post them right away. Thanks for the assistance!

Tony
 
Disable the watchdog, then use the probe to see what the 68K is doing. Free running, or stuck in halt?

If you put the new 68K in a socket then remove it and probe address lines to see if something else is trying to drive them.
 
Hi tendril, thanks for replying!

With J2 jumpered to stop watchdog, the 68k Halt pin is Low.

Here are the pin readings at the 68k while watchdog is disabled:
1-14 High
15 Pulsing
16, 17 Low
18-24 High
25 Low
26, 27 High
28 Low
29-32 High
33-44 No Signal
45-50 High
51, 52 No Signal
53 Low
54-64 High

In addition, here are the pin readings at the ROM while watchdog is disabled:
1 High
2 Low
3-10 High
11 Low
12-20 High
21-24 High
25-29 No Signal
30 Low
31-37 No Signal
38-40 High

I didn't have a socket for the 68k, but before I soldered in the new 68k, i checked the address lines on the ROM and they were the same as above (not low, not high, just not there and weakly blipping with watchdog reset).

Tony
 
I was hoping Tendril or someone else could provide some guidance based off of my latest measurements. I've been stuck for awhile at this point. Can't seem to find the source of the bad signal levels on the address lines. I'm hoping there is something else I can measure or test to help locate the issue.

I'm probably completely wrong, but it feels like the address lines are shorted or possibly shorted to ground or maybe two chips are driving the lines at the same time (one high, one low)? Also, the lack of activity on the address lines is puzzling. Even the data lines are solid high, no pulsing. I thought originally the Halt line was ok with a low, but I think a low means the 68k is halted? Does a halt leave address pins in an "open collector" state? I might have that terminology wrong, but left in a state of no signal (or weak signal)?

Tony
 
When /HALT is active (low), the address and data bus are set to a high-impedance state. /HALT is bidirectional: both the NEO-B1 and the 68000 itself can assert it. For instance, if the 68000 encounters a double bus fault, such as in the case of reading bad instruction data, it will assert /HALT.
 
Forgot to reply sorry!

You said you checked all data and address lines for continuity from ROM/RAM to CPU - that's good - but did you check if any lines were shorted together?

I had a 4 slot were D3-4-5 were shorted together - took ages to find as it was a tiny bit of solder at the pads where they go to one of the custom chips.

I wonder if the 'weak' address line is a short to somewhere.
 
Checked the address and data lines for shorts and did not find any. I reconfirmed that the Halt pin on the 68k and the C0 chips is low. BR and BERR are high. Checked address and data pins for shorts to ground and they were all good at the BIOS and 68k. I did notice while checking the 68k pins to ground that the average resistance was around 500-600ohms. On another 6 slot I have, the 68k pins averaged about 1k to ground. Seems odd, but the 2 6 slots I have are slightly different in the board layout. On this bad board, I have a resistor soldered across two pins on chip B5 and on my other 6 slot, there is a resistor soldered on the board in an actual location made for it. So there must be different revisions of the 6 slot PCB.

Anyway, I'm still scratching my head. Not giving up on this though. I'm determined to make this board work.
 
And you checked the reset to the 68K is ok too? (low then high for a short time before presumably going back to low on the halt). Just verify it's not stuck low all the time from boot?
 
Just double checked the RESET pin on the 68k and it does toggle from low to high on each reset from the watchdog. When I jump J2, it then stays high. HALT is still solid low all of the time.

Probably a dumb question, but is there any way to force the HALT High without lifting the 68k pin? Is the HALT line only connected between the 68k and C0 or is there something else on that line?

Besides 68k, ROM, RAM and a few NEO chips, are there any logic ICs I should be re-checking?
 
Just double checked the RESET pin on the 68k and it does toggle from low to high on each reset from the watchdog. When I jump J2, it then stays high. HALT is still solid low all of the time.

Probably a dumb question, but is there any way to force the HALT High without lifting the 68k pin? Is the HALT line only connected between the 68k and C0 or is there something else on that line?

Besides 68k, ROM, RAM and a few NEO chips, are there any logic ICs I should be re-checking?

As I mentioned above, it might actually be the 68000 that's asserting the HALT line, in response to an irrecoverable fault condition. I'd be curious to know if /SROMOE is being correctly asserted and valid instruction are being fetched from the BIOS ROM.
 
To use an example, this is a logic analyzer trace from a Jackie Chan PCB where the program ROM /CE line is not being asserted and the 68000 subsequently goes into a HALT state after the reset vector fetch. Something similar could be happening in your case?
 

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I have a 4 slot coming monday.. So i have been reading a ton of repair threads...

This sounds similar to one where the bios rom was corrupted.

Take this with a grain of salt
 
Didn't want to leave folks hanging... I'm currently getting a logic analyzer set up to capture a similar trace to what Phil presented. I don't have a true logic analyzer, so i'm trying to put one together with one of those cheap Cyprus units using Pulseview. Almost there, so hoping to post something within the next few days.

The BIOS ROM chip is good, I'm using UniBIOS and it works fine with other MVS boards I have lying around. Also tried the Diagnostic ROM with no luck.

More to come....

Tony
 
Cool trossi, keep us posted, I just thought I would throw that out there.

Got mine in and working, but no sound...
 
Didn't want to leave folks hanging... I'm currently getting a logic analyzer set up to capture a similar trace to what Phil presented. I don't have a true logic analyzer, so i'm trying to put one together with one of those cheap Cyprus units using Pulseview. Almost there, so hoping to post something within the next few days.

More to come....

Tony

I eagerly await the next part :)
 
Here we go...

Was able to get something out of my setup.... See attached screenshot of my capture.

Wasn't sure what to set pulseview to so I used: 1M samples, 1Mhz

Hooked in to:
68k: CLK, HALT, RESET, A1 and D0
ROM: CE, A0, D0

Looks like CLK is there and good, Halt is toggling, Reset is toggling, A1 is stuck High, ROM CE is doing something but not sure what, ROM A0 and D0 are stuck high and 68k D0 is stuck high.

Remember that the watchdog is resetting a couple times a second.

Let me know if you would like to see any other pins or a different capture setting.

Tony
 

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I doubt it will help but i posted line schematics for the mvs 1 slot in my repair thread.
 
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