Got a conversion board in that I suspect will have multiple problems. There is a lot of previous work that has resulted in damaged traces, which have been kludged back together with jumper wires. Make some popcorn for this one.
First, I remove the Alpha processor and hook up the Fluke. The bus test passes, as do the program RAM and ROM tests. Note that the ROMs at 1L and 1M/N can be tested normally, but the ones at 1N/P and 1Q have address line 13 controlled by MMUPAGE0, so they must be tested in two steps. This is done by writing different values to address 1740 to set MMUPAGE0 and MMUPAGE1 and then getting the checksum for ROM2 (2000-3FFF). Also note that the WDDIS must be grounded so the watchdog does not reset the LS74 flip flop @ 2N that sets MMUPAGE0 and MMUPAGE1.
Some may ask why not simply remove the chips and test them with a reader. You could do that, but I'd rather leave them in place and see what the CPU is actually reading (which tests sockets, traces, and all the supporting chips like decoders and buffers). Gotta justify the cost of the Fluke and pod!
Here's how writing to address 1740 sets the flip-flop to access the two halves of the two ROM chips at 1N/P and 1Q. Accessing that particular address means that the CPU will momentarily set address bits 12, 10, 9, 8, and 6 to a high logic state (since hex 1740 = 0001 0111 0100 0000 binary). Those address lines (after being buffered by 2Q and 2P) go many places, but we're interested in what happens when they hit the LS139 at 4N and the LS138 at 5N:
from sheet 5B
A high on buffered address lines 9 and 10 will go into pins 2 and 3 of the LS139, causing it to output a low on pin 7 (the data sheet tells you so). That goes over to the LS138 pin 5, which will enable that chip when pin 4 is also low... which happens when the CPU is writing. Other inputs are A, B, and C coming from address bits 6, 7, and 8. Six and eight are high, which causes the LS138 to make output pin Y5 low. That is the /MMU signal. Address decoding at its finest!
The MMU acts as the clock signal for the flip-flop at 2N, which is permanently in preset mode due to the +5v at pins 4 and 10. Preset means it will take whatever data is present on its input pin (D) and set and hold its output pins (Q) at that level when the clock is pulsed. What data is present on the input pins? Pin 12 is connected to (buffered) data bus line 0, while pin 2 gets BD1.
Putting this all together, when writing a zero to address 1740 the address bits cause a pulse on /MMU so the logic lows on BD0 and BD1 are transferred and held on MMUPAGE0 and MMUPAGE1 (and the LS74 also creates /MMUPAGE1 at pin 6 = the opposite of MMUPAGE1 eg logic high). Other values written to 1740 will set the outputs as follows:
0 = binary 00 results in MMUPAGE1 = 0 and MMUPAGE0 = 0
1 = binary 01 results in MMUPAGE1 = 0 and MMUPAGE0 = 1
2 = binary 10 results in MMUPAGE1 = 1 and MMUPAGE0 = 0
3 = binary 11 results in MMUPAGE1 = 1 and MMUPAGE0 = 1
These signals are then fed into the pins of the ROMs themselves. When MMUPAGE1 is low /MMUPAGE1 is high so 1Q is enabled and 1N/P is not. Meanwhile MMUPAGE0 is controlling address bit 13 of the ROM chip, so when it is low you get data from the lower half of the chip, and when it is high you get the upper half. So:
1740 = 0, ROM TEST @ 2000-3FFF gets the lower half of 1Q whose Fluke signature is 2057 (v3) or CA55 (v2)
1740 = 1, ROM TEST @ 2000-3FFF gets the upper half of 1Q sig FD30 (v3) or 52EA (v2)
1740 = 2, ROM TEST @ 2000-3FFF gets the lower half of 1N/P, sig C37C (v3) or 4876 (v2)
1740 = 3, ROM TEST @ 2000-3FFF gets the upper half of 1N/P, sig 2DF2 (v3) or D0B8 (v2)
First, I remove the Alpha processor and hook up the Fluke. The bus test passes, as do the program RAM and ROM tests. Note that the ROMs at 1L and 1M/N can be tested normally, but the ones at 1N/P and 1Q have address line 13 controlled by MMUPAGE0, so they must be tested in two steps. This is done by writing different values to address 1740 to set MMUPAGE0 and MMUPAGE1 and then getting the checksum for ROM2 (2000-3FFF). Also note that the WDDIS must be grounded so the watchdog does not reset the LS74 flip flop @ 2N that sets MMUPAGE0 and MMUPAGE1.
Some may ask why not simply remove the chips and test them with a reader. You could do that, but I'd rather leave them in place and see what the CPU is actually reading (which tests sockets, traces, and all the supporting chips like decoders and buffers). Gotta justify the cost of the Fluke and pod!
Here's how writing to address 1740 sets the flip-flop to access the two halves of the two ROM chips at 1N/P and 1Q. Accessing that particular address means that the CPU will momentarily set address bits 12, 10, 9, 8, and 6 to a high logic state (since hex 1740 = 0001 0111 0100 0000 binary). Those address lines (after being buffered by 2Q and 2P) go many places, but we're interested in what happens when they hit the LS139 at 4N and the LS138 at 5N:
from sheet 5B
A high on buffered address lines 9 and 10 will go into pins 2 and 3 of the LS139, causing it to output a low on pin 7 (the data sheet tells you so). That goes over to the LS138 pin 5, which will enable that chip when pin 4 is also low... which happens when the CPU is writing. Other inputs are A, B, and C coming from address bits 6, 7, and 8. Six and eight are high, which causes the LS138 to make output pin Y5 low. That is the /MMU signal. Address decoding at its finest!
The MMU acts as the clock signal for the flip-flop at 2N, which is permanently in preset mode due to the +5v at pins 4 and 10. Preset means it will take whatever data is present on its input pin (D) and set and hold its output pins (Q) at that level when the clock is pulsed. What data is present on the input pins? Pin 12 is connected to (buffered) data bus line 0, while pin 2 gets BD1.
Putting this all together, when writing a zero to address 1740 the address bits cause a pulse on /MMU so the logic lows on BD0 and BD1 are transferred and held on MMUPAGE0 and MMUPAGE1 (and the LS74 also creates /MMUPAGE1 at pin 6 = the opposite of MMUPAGE1 eg logic high). Other values written to 1740 will set the outputs as follows:
0 = binary 00 results in MMUPAGE1 = 0 and MMUPAGE0 = 0
1 = binary 01 results in MMUPAGE1 = 0 and MMUPAGE0 = 1
2 = binary 10 results in MMUPAGE1 = 1 and MMUPAGE0 = 0
3 = binary 11 results in MMUPAGE1 = 1 and MMUPAGE0 = 1
These signals are then fed into the pins of the ROMs themselves. When MMUPAGE1 is low /MMUPAGE1 is high so 1Q is enabled and 1N/P is not. Meanwhile MMUPAGE0 is controlling address bit 13 of the ROM chip, so when it is low you get data from the lower half of the chip, and when it is high you get the upper half. So:
1740 = 0, ROM TEST @ 2000-3FFF gets the lower half of 1Q whose Fluke signature is 2057 (v3) or CA55 (v2)
1740 = 1, ROM TEST @ 2000-3FFF gets the upper half of 1Q sig FD30 (v3) or 52EA (v2)
1740 = 2, ROM TEST @ 2000-3FFF gets the lower half of 1N/P, sig C37C (v3) or 4876 (v2)
1740 = 3, ROM TEST @ 2000-3FFF gets the upper half of 1N/P, sig 2DF2 (v3) or D0B8 (v2)
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