LyonsArcade
Well-known member
Hi guys!
I'm trying to learn to troubleshoot boards, and have a Defender board I'm working on. I've narrowed the problem to the board, and I believe i've even narrowed the problem to a pin, so I thought I'd ask for help here and see if any of the old timers can tell me what's going on.
I've been following the troubleshooting guide that williams put out, the recap cpu logic probe guide.
My problem is in the Page 0 Decoder circuit. 4K chip, a 74139. The way the schematics read, the chip gets an input from the data buss at A10/A11, pin 2 and 3 on the chip. This pulses pins 4,5,6,7. 4 enables the color ram, check. That's pulsing. 5 enables the CMOS ram, check, that ones pulsing as well. 7 enables the interface board, check, that one's pulsing. Pin 6 should pulse (as best as I can tell) and enable the Vertical Count Buffer circuit, it's not pulsing.
The monitor has sync issues, probably since this Vertical Count Buffer circuit isn't kicking in. I'm not getting a pulse at Pin 6 on 4K, and I switched (and socketed) that 74139 twice to be sure. Because of that I'm not getting a pulse at pin 5 on 5P, which in turn isn't turning on pin 6, which in turn isn't pulsing 3D to get the vertical count buffer all started.
I'm getting a pulse at 2F where a10/a11 enter the buss and also of course at 4K pin 2 and 3 where a10/a11 exit the bus, plus I've switched that chip, so I'm just wondering what I'm missing here about why that isn't turning on. C800 is the address that when accessed, asserts that pin's output, so I'm thinking maybe the mpu is never accessing that address? Does that sound right?
Thanks for any help, I'm trying to learn this stuff but still have a LONNNNNG way to go.
I'm trying to learn to troubleshoot boards, and have a Defender board I'm working on. I've narrowed the problem to the board, and I believe i've even narrowed the problem to a pin, so I thought I'd ask for help here and see if any of the old timers can tell me what's going on.
I've been following the troubleshooting guide that williams put out, the recap cpu logic probe guide.
My problem is in the Page 0 Decoder circuit. 4K chip, a 74139. The way the schematics read, the chip gets an input from the data buss at A10/A11, pin 2 and 3 on the chip. This pulses pins 4,5,6,7. 4 enables the color ram, check. That's pulsing. 5 enables the CMOS ram, check, that ones pulsing as well. 7 enables the interface board, check, that one's pulsing. Pin 6 should pulse (as best as I can tell) and enable the Vertical Count Buffer circuit, it's not pulsing.
The monitor has sync issues, probably since this Vertical Count Buffer circuit isn't kicking in. I'm not getting a pulse at Pin 6 on 4K, and I switched (and socketed) that 74139 twice to be sure. Because of that I'm not getting a pulse at pin 5 on 5P, which in turn isn't turning on pin 6, which in turn isn't pulsing 3D to get the vertical count buffer all started.
I'm getting a pulse at 2F where a10/a11 enter the buss and also of course at 4K pin 2 and 3 where a10/a11 exit the bus, plus I've switched that chip, so I'm just wondering what I'm missing here about why that isn't turning on. C800 is the address that when accessed, asserts that pin's output, so I'm thinking maybe the mpu is never accessing that address? Does that sound right?
Thanks for any help, I'm trying to learn this stuff but still have a LONNNNNG way to go.