Happy New Year to all Computer Space Enthusiasts!
The first Computer Space FPGA release is now available for download.
It has been developed primarily to understand the inner workings of the Computer Space game logic. The emulator can also serve the purpose of game preservation as the schematics have been copied "wire by wire" and "component by component"/"gate by gate" and hence represents a very close realization of the original, except for sound
generation which in this solution is based on audio samples.
The emulator has been developed for Terasic Altera DE0 Nano, which is a low cost FPGA board.
Sound is preloaded as (signed) 8 bit, 11 kHz - using a first order sigma delta DAC output solution.
Video options includes original Computer Space video type and interlaced NTSC standard (for play on eg LCD screens).
In order to see the video, hear the sound and play the game – a very simple interface has to be built consisting of a handful resistors and a capacitor. Schematics provided.
There are three files:
1) jic-file (just "simply" load the file on the de0 nano and CS is "permanently" configured)
2) vhdl – all vhdl files (best viewed in a vhdl editor or similar)
3) conceptual interface schematics
The full set of altera quartus files, including project file and sound files will be linked separately.
A higher end version targeting Terasic Altera DE1 will be released in a little while. It will feature the option to have signed 16 bit audio @ 48kHz, using an onboard commercial audio codec chip. This will however require the user to load its own audio sample set into a flash memory.
I also believe the solution can be adopted for the Altera Max 10 chip – which would be a true single chip solution as the Max 10 features on-chip oscillator, on-chip flash and on-chip configuration memory.
Special credit to Mike Salay (KLOV: road.runner) and computerspacefan.com for helping out with real board measurements and basic sound samples.
Enjoy!
The first Computer Space FPGA release is now available for download.
It has been developed primarily to understand the inner workings of the Computer Space game logic. The emulator can also serve the purpose of game preservation as the schematics have been copied "wire by wire" and "component by component"/"gate by gate" and hence represents a very close realization of the original, except for sound
generation which in this solution is based on audio samples.
The emulator has been developed for Terasic Altera DE0 Nano, which is a low cost FPGA board.
Sound is preloaded as (signed) 8 bit, 11 kHz - using a first order sigma delta DAC output solution.
Video options includes original Computer Space video type and interlaced NTSC standard (for play on eg LCD screens).
In order to see the video, hear the sound and play the game – a very simple interface has to be built consisting of a handful resistors and a capacitor. Schematics provided.
There are three files:
1) jic-file (just "simply" load the file on the de0 nano and CS is "permanently" configured)
2) vhdl – all vhdl files (best viewed in a vhdl editor or similar)
3) conceptual interface schematics
The full set of altera quartus files, including project file and sound files will be linked separately.
A higher end version targeting Terasic Altera DE1 will be released in a little while. It will feature the option to have signed 16 bit audio @ 48kHz, using an onboard commercial audio codec chip. This will however require the user to load its own audio sample set into a flash memory.
I also believe the solution can be adopted for the Altera Max 10 chip – which would be a true single chip solution as the Max 10 features on-chip oscillator, on-chip flash and on-chip configuration memory.
Special credit to Mike Salay (KLOV: road.runner) and computerspacefan.com for helping out with real board measurements and basic sound samples.
Enjoy!



