Thank you @HudsonArcade. Just to make sure I understand - you are referring to RD (CPU Pin 21) and WR (CPU Pin 22)? Which CPU pin would correspond to Enable?
Maybe I am misinterpreting, but are you saying that these LO pulses are a result of the CPU waiting for a response on those pins - but not receiving one? This is intriguing because as best we can tell, the two nearby 27256 PROMs (Device 13D and 14D) are never being powered up and enabled. The Chip Enable (CE) signals, and Vpp (+5V), for those two PROMs are coming in on the BANK 0, BANK 1 and BANK 2 lines from the 74LS273 (Device 5B) - which is also tied to the same Data Bus in question. Not having access to the boards at the moment - I am wondering if the 74LS273 is bad?
This definitely gives us a new perspective with which to proceed.
Thanks again.
Maybe I am misinterpreting, but are you saying that these LO pulses are a result of the CPU waiting for a response on those pins - but not receiving one? This is intriguing because as best we can tell, the two nearby 27256 PROMs (Device 13D and 14D) are never being powered up and enabled. The Chip Enable (CE) signals, and Vpp (+5V), for those two PROMs are coming in on the BANK 0, BANK 1 and BANK 2 lines from the 74LS273 (Device 5B) - which is also tied to the same Data Bus in question. Not having access to the boards at the moment - I am wondering if the 74LS273 is bad?
This definitely gives us a new perspective with which to proceed.
Thanks again.
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