8080a cpu questions

andykmv

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the 8080 datasheets dont give me enough information on the functioning of the HOLD and READY signals and their effect on the CPU.

context: SI clone pcb doesnt boot properly. i noticed a few of the signals into the CPU were in a steady state (not toggling) and, I also noticed that the CPU databus pins (D0-D7) look to be in HiZ state - i will have to confirm if the steady signals were the the HOLD and/or READY signals.

related posts:
http://forums.arcade-museum.com/show...19&postcount=1
http://forums.arcade-museum.com/showpost.php?p=1616786&postcount=1

the questions i have in mind are:

1. READY/WAIT (CPU pins 23, 24)
this signal comes from a 74ls74 location E3 pin 9, on the Midway SI schematic/layout, C1 pin 9 on the GW layout.
Q: if the READY line is held LOW does this effectively halt the cpu ? - does this put the databus in HiZ ?

2. HOLD/HLDA (pins 13,21)
this signal comes from a 74ls86? location A4 pin 3, on the Midway SI schematic/layout.
if the HOLD line is held HIGH does this effectively halt the cpu ?
- the datasheet suggests this does put the databus in HiZ under certain conditions.
 
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the 8080 datasheets dont give me enough information on the functioning of the HOLD and READY signals and their effect on the CPU.

context: SI clone pcb doesnt boot properly. i noticed a few of the signals into the CPU were in a steady state (not toggling) and, I also noticed that the CPU databus pins (D0-D7) look to be in HiZ state - i will have to confirm if the steady signals were the the HOLD and/or READY signals.

related posts:
http://forums.arcade-museum.com/show...19&postcount=1
http://forums.arcade-museum.com/showpost.php?p=1616786&postcount=1

the questions i have in mind are:

1. READY/WAIT (CPU pins 23, 24)
this signal comes from a 74ls74 location E3 pin 9, on the Midway SI schematic/layout.
Q: if the READY line is held LOW does this effectively halt the cpu ? - does this put the databus in HiZ ?

2. HOLD/HLDA (pins 13,21)
this signal comes from a 74ls86? location A4 pin 3, on the Midway SI schematic/layout.
if the HOLD line is held HIGH does this effectively halt the cpu ?
- the datasheet suggests this does put the databus in HiZ under certain conditions.

IIRC READY is used when reading from slow devices to make the cpu wait longer for the
data to be placed on the bus by the external device. My guess is it main use is during
read cycles, so yeah, the 8080 should not be driving the data bus during a read cycle.
but it would be presenting an address on the addr bus.

The HOLD is a request to the CPU to get off the bus, but the CPU will not get off
the bus until its in certain states, as in this does not necessarily happen immediately.
When it finally gives up the bus, then the CPU drives back the HLDA acknowledge
indicating that the bus is now available (HiZ) and that some other device can now
use the bus. I would guess both the data bus and address bus are hiz at this
point until the requester takes away the hold.
 
thanks steve, that helps and i will look more closely at these areas. :)

trying to locate the relevant ics now.

1. 74ls74 location C1 pin 9 on the GW layout (E3 pin 9, on the Midway SI schematic/layout) connects to the READY input on the 8080a CPU pin 23.
 
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